PCB layout is a key element of ESD protection, rational PCB Design can reduce troubleshooting and rework caused by unnecessary costs. In PCB design, the use of transient voltage suppress device (TVS) diode for ESD strikes to suppress the direct charge injection, so the PCB design is more important is to overcome the discharge current electromagnetic interference (EMI) electromagnetic field effects. The following will provide ESD protection can be optimized PCB design guidelines.
　　Circuit loop
　　Current into the circuit through the sensor loop, the loop is closed, and with changes in magnetic flux. Current amplitude proportional to the area with the ring. Larger loop contains more magnetic flux, which induces a strong in-circuit current. Therefore, we must reduce the loop area.
　　The most common loop formed by the power supply and ground. Possible conditions, can be used with the power and ground layers of multi-layer PCB design. Multi-layer circuit board will not only power and ground to minimize the loop area between, but also reduces EMI ESD pulses generated by high-frequency electromagnetic fields.
　　If you can not use multi-layer circuit board, then used for power and ground lines must be connected to the grid shown in Figure 2. Grid connection can play the role of power and ground layers, vias connecting layers of printed lines in each direction vias within the interval should be 6 cm. In addition, the wiring, the power and ground traces as close as possible can reduce the loop area.
　　Reduce the induced current loop area and another way is to reduce the interconnection between devices in parallel pathways.
　　Must be longer than 30 cm when the signal cable, you can use to protect line, a better approach is to be placed in the ground near the signal line. Signal lines should be protected from the line or ground line layer 13 mm or less.
　　Sensitive components of each signal line length (> 30 cm) power cord with ground wire or cross layout. Cross-connection must be at regular intervals from top to bottom or left to right layout.
　　The length of the circuit connection
　　Long signal lines can also become an antenna to receive ESD pulse energy, try a shorter signal lines can reduce the signal line ESD electromagnetic field as a receiver antenna efficiency. As the interconnection of devices on the adjacent position to reduce the interconnect trace length.
　　To charge injection
　　ESD discharge on the ground floor directly cause damage to sensitive circuits. In the use of TVS diodes but also use one or more high-frequency bypass capacitors, these capacitors placed in the vulnerable components of the power supply and ground. Bypass capacitor to reduce the charge injection to keep the power and ground port voltage difference.
　　TVS induced current shunt to keep the TVS clamping voltage potential difference. TVS and capacitors should be placed away from the protected IC as close as possible to ensure that TVS and capacitor pin to ground path length of the shortest, to reduce the parasitic inductance effect.
　　Connector must be installed to the layer of copper on the PCB. Ideally, copper, platinum layer to isolate the PCB's ground plane, connected by short-term and pad.
　　Other criteria for PCB Design:
　　Arrangements to avoid the edge of the PCB important signal lines, such as clock and reset signals;
　　The unused portion on the PCB ground plane is set;
　　Chassis ground and signal line interval of at least 4 mm;
　　Chassis ground to maintain the aspect ratio of less than 5:1 to reduce the inductance;
　　TVS diode to protect with all external connections;
　　Parasitic inductance in the circuit protection TVS diode parasitic inductance in the path during an ESD event will have a severe voltage overshoot. Despite the use of TVS diodes, due to the induced voltage across the load inductance VL = L × di / dt, excessive overshoot voltage may still be protected more than the threshold voltage of the IC damage.
　　Protection circuit to withstand the total voltage TVS diode clamping voltage and the voltage of the parasitic inductance and, VT = VC + VL. ESD induced current in a transient period of time can be less than 1ns peak (according to IEC 61000-4-2), assumed the lead inductance per inch 20nH, a quarter-inch length, the voltage overshoot is 50V/10A pulse. Experience diversion channel design criteria is designed to be as short as possible to reduce the parasitic inductance effect.
　　All inductive ground return path must be considered, TVS and the protected path between the signal line, and connector access to the TVS device. The signal line should be protected be connected directly to the ground, without ground plane, the ground loop connections should be as short as possible. TVS diode protection circuit ground and the distance between the ground should be as short as possible, in order to reduce the parasitic inductance of the ground plane.
　　Finally, TVS device should be as close as possible to reduce access to the connector near the line of transient coupling. Although there is no direct access to the connector, but the secondary effects of radiation can lead to other parts of the circuit board work disorder.
　　These are the PCB Design in ESD suppression techniques, and I hope to be helpful.